Layout-Based Dual-Cell-Aware Tests

Tse Wei Wu, Dong Zhen Lee, Kai-Chiang Wu, Yu Hao Huang, Ying Yen Chen, Po Lin Chen, Mason Chern, Jih Nung Lee, Shu Yi Kao, Chia-Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

Original languageEnglish
Title of host publication2019 IEEE 37th VLSI Test Symposium, VTS 2019
PublisherIEEE Computer Society
ISBN (Electronic)9781728111704
StatePublished - 1 Apr 2019
Event37th IEEE VLSI Test Symposium, VTS 2019 - Monterey, United States
Duration: 23 Apr 201925 Apr 2019

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference37th IEEE VLSI Test Symposium, VTS 2019
CountryUnited States

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