Layout-aware analog synthesis environment with yield consideration

Hsin Ju Chang, Yen Lung Chen, Conan Yeh, Chien-Nan Liu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

With shrinking device size in deep submicron process, many non-ideal effects impact circuit performances critically. Since those effects are often not considered in traditional analog synthesis tools, several sizing-layout iterations are still required to reach the desired performance and design yield. In this paper, an integrated analog synthesis tool is presented to consider the process variation, layout effects, and final layout generation simultaneously, with a user-friendly GUI to help users complete the design flow efficiently. With the consideration of those non-ideal effects in early design stages, blind design margins and time-consuming re-design cycles can be avoided in the proposed tool, which significantly reduces the design overhead. As shown in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds and effectively guarantees the post-layout performance and design yield with less hardware cost.

Original languageEnglish
Title of host publicationProceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PublisherIEEE Computer Society
Pages589-593
Number of pages5
ISBN (Electronic)9781479975815
DOIs
StatePublished - 13 Apr 2015
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: 2 Mar 20154 Mar 2015

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2015-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period2/03/154/03/15

Keywords

  • Analog synthesis
  • Layout-aware sizing
  • Yield-aware sizing

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