An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 μm LATID n-MOSFET. In the experiment, the device was subject to a DC voltage stress to generate interface traps. Based on our proposed bandtrap-band tunneling, the increased drain leakage current can be adequately described by an analytical expression of ΔId=Aexp(-Bit/F) with a Bit of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.
|State||Published - 1 Jan 1994|
|Event||1994 International Electron Devices and Materials Symposium, EDMS 1994 - Hsinchu, Taiwan|
Duration: 12 Jul 1994 → 15 Jul 1994
|Conference||1994 International Electron Devices and Materials Symposium, EDMS 1994|
|Period||12/07/94 → 15/07/94|