Latehup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test

Ming-Dou Ker*, Cheng Cheng Yen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Two different on-chip power-rail electrostatic discharge (ESD) protection circuits, (1) with NMOS and PMOS feedback; and (2) with cascaded PMOS feedback, have been designed and fabricated in a 0.18-μm CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a microelectronics system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. The susceptibility of power-rail ESD clamp circuits with the additional board-level noise Alter to the system-level ESD test is also investigated. To meet high system-level ESD specifications, the chip-level ESD protection design should be considered with the transient noise during system-level ESD stress.

Original languageEnglish
Title of host publicationIEEE International Symposium on Electromagnetic Compatibility, EMC 2007
DOIs
StatePublished - 1 Dec 2007
EventIEEE International Symposium on Electromagnetic Compatibility, EMC 2007 - Honolulu, HI, United States
Duration: 9 Jul 200713 Jul 2007

Publication series

NameIEEE International Symposium on Electromagnetic Compatibility
ISSN (Print)1077-4076

Conference

ConferenceIEEE International Symposium on Electromagnetic Compatibility, EMC 2007
CountryUnited States
CityHonolulu, HI
Period9/07/0713/07/07

Keywords

  • Board-level noise filter
  • Electrostatic discharge (ESD)
  • Power clamp circuits
  • System-level ESD
  • Test

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    Ker, M-D., & Yen, C. C. (2007). Latehup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test. In IEEE International Symposium on Electromagnetic Compatibility, EMC 2007 [4305743] (IEEE International Symposium on Electromagnetic Compatibility). https://doi.org/10.1109/ISEMC.2007.163