Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ming-Dou Ker; Tain Shun Wu

doi:10.1016/S0038-1101(97)87368-6

Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ming-Dou Ker^*, Tain Shun Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

Abstract

A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

Original language	English
Pages (from-to)	1329-1336
Number of pages	8
Journal	Solid-State Electronics
Volume	41
Issue number	9
DOIs	https://doi.org/10.1016/S0038-1101(97)87368-6
State	Published - 1 Jan 1997

Access to Document

10.1016/S0038-1101(97)87368-6

Link to publication in Scopus

Fingerprint Dive into the research topics of 'Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs'. Together they form a unique fingerprint.

Cite this

@article{02ca1a0e185d494a80f7bb5d119cfab6,

title = "Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs",

abstract = "A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.",

author = "Ming-Dou Ker and Wu, {Tain Shun}",

year = "1997",

month = jan,

day = "1",

doi = "10.1016/S0038-1101(97)87368-6",

language = "English",

volume = "41",

pages = "1329--1336",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

number = "9",

}

TY - JOUR

T1 - Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

AU - Ker, Ming-Dou

AU - Wu, Tain Shun

PY - 1997/1/1

Y1 - 1997/1/1

N2 - A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

AB - A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

UR - http://www.scopus.com/inward/record.url?scp=0031232673&partnerID=8YFLogxK

U2 - 10.1016/S0038-1101(97)87368-6

DO - 10.1016/S0038-1101(97)87368-6

M3 - Article

AN - SCOPUS:0031232673

VL - 41

SP - 1329

EP - 1336

JO - Solid-State Electronics

JF - Solid-State Electronics

SN - 0038-1101

IS - 9

ER -