Abstract
A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.
Original language | English |
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Pages (from-to) | 1329-1336 |
Number of pages | 8 |
Journal | Solid-State Electronics |
Volume | 41 |
Issue number | 9 |
DOIs | |
State | Published - 1 Jan 1997 |