Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ming-Dou Ker; Tain Shun Wu

doi:10.1016/S0038-1101(97)87368-6

Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ming-Dou Ker^*, Tain Shun Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

Abstract

A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

Original language	English
Pages (from-to)	1329-1336
Number of pages	8
Journal	Solid-State Electronics
Volume	41
Issue number	9
DOIs	https://doi.org/10.1016/S0038-1101(97)87368-6
State	Published - 1 Jan 1997

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abstract = "A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.",

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AU - Wu, Tain Shun

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N2 - A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

AB - A latchup-free on-chip input ESD protection circuit with a concept of full protection against ESD damage is proposed. Tnnhe four modes of ESD stresses on an input pad are one-by-one protected by four effective ESD discharging paths in this proposed ESD protection circuit to avoid unexpected ESD damage. This ESD protection circuit was included in a 0.8 μm cell library to successfully provide high ESD reliability for input pads of CMOS ASICs within a small layout area.

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JO - Solid-State Electronics

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Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Abstract

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