A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurrence of latchup without any process modification or extra fabrication cost. It is suitable for whole-chip latchup prevention of bulk CMOS integrated circuits. This proposed latchup current self-stop methodology and circuit have been verified in a 0.5-μm 1P3M bulk CMOS process.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 2002|