LASER - Layout-aware Analog Synthesis Environment on Laker

Yu Ching Liao, Yen Lung Chen, Xian Ting Cai, Chien-Nan Liu, Tai Chen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

In modern technology, layout effects have more and more impacts on circuit performance. However, most of the existing analog automation tools consider the circuit sizing and layout generation in two separate steps, which often result in time-consuming sizing-layout iterations. In this paper, a layout-aware analog synthesis tool is presented to generate the required designs from specifications to layout through a user-friendly GUI. In order to provide a strong link between sizing and layout steps, a parasitic-aware circuit sizing flow is proposed based on a flexible layout template to prevent the performance from failing to meet the specifications after layout. Routability-aware analog placement is then performed with a simple routing algorithm to generate the corresponding layout with minimized cost. As demonstrated in the experimental results, this analog synthesis tool is able to generate the required circuits in seconds with high quality layouts and effectively guarantees the post-layout performance with less over-design.

Original languageEnglish
Title of host publicationGLSVLSI 2013 - Proceedings of the ACM International Conference of the Great Lakes Symposium on VLSI
Pages107-112
Number of pages6
DOIs
StatePublished - 30 May 2013
Event23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013 - Paris, France
Duration: 2 May 20133 May 2013

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference23rd ACM International Conference of the Great Lakes Symposium on VLSI, GLSVLSI 2013
CountryFrance
CityParis
Period2/05/133/05/13

Keywords

  • analog
  • parasitic-aware sizing
  • routability-aware placement
  • synthesis

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