Large-Signal 2T, 1C DRAM Cell: Signal and Layout Analysis

W. H. Henkels, Wei Hwang

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

This paper presents a general signal and layout analysis for the two-transistor, one-capacitor DRAM cell. The 2T, 1C configuration enables significantly larger, typically > 3×, raw sense-signal than is achievable in conventional IT, 1C cells. In general, stray capacitances at the capacitor nodes further increase the signal level; an exact analytic formula is derived in this case, including the dependence upon bitline precharge level. With trench technology, the 2T, 1C cell occupies 25-30% more area than a corresponding folded-bitline IT, 1C cell; an implementation employing a buried strap is proposed. Maximization of array density requires multiplexing bitlines to sense amps.

Original languageEnglish
Pages (from-to)829-832
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number7
DOIs
StatePublished - 1 Jan 1994

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