Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Jer Yi Lin, Po Yi Kuo*, Ko Li Lin, Chun Chieh Chin, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (ION/IOFF) ∼ 7 × 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

Original languageEnglish
Article number7676340
Pages (from-to)4998-5003
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume63
Issue number12
DOIs
StatePublished - 1 Dec 2016

Keywords

  • 3-D ICs
  • gate-all-around (GAA)
  • junctionless (JL)
  • nanowire (NW)
  • polycrystalline-Si (poly-Si) thin-film transistors

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