Jointly designed nonbinary LDPC convolutional codes and memory-based decoder architecture

Chia Lung Lin*, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this paper, a design approach for architectureaware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy- efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach BER = 10-5 at SNR = 0.9 dB and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications.

Original languageEnglish
Article number07277127
Pages (from-to)2523-2532
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume62
Issue number10
DOIs
StatePublished - 1 Oct 2015

Keywords

  • Convolutional codes
  • Error correction
  • Low-density parity-check (NB-LDPC) convolutional codes VLSI
  • Nonbinary

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