Joint logic restructuring and pin reordering against NBTI-induced performance degradation

Kai-Chiang Wu*, Diana Marculescu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

47 Scopus citations

Abstract

Negative Bias Temperature Instability (NBTI), a PMOS aging phenomenon causing significant loss on circuit performance and lifetime, has become a critical challenge for temporal reliability concerns in nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate a design optimization flow considering NBTI effects at the early stages. In this paper, we present a novel framework using joint logic restructuring and pin reordering to mitigate NBTI-induced performance degradation. Based on detecting functional symmetries and transistor stacking effects, the proposed methodology involves only wire perturbation and introduces no gate area overhead at all. Experimental results reveal that, by using this approach, on average 56% of performance loss due to NBTI can be recovered. Moreover, our methodology reduces the number of critical transistors remaining under severe NBTI and thus, transistor resizing can be applied to further mitigate NBTI effects with low area overhead.

Original languageEnglish
Title of host publicationProceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
Pages75-80
Number of pages6
DOIs
StatePublished - 22 Oct 2009
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice, France
Duration: 20 Apr 200924 Apr 2009

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

Conference2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CountryFrance
CityNice
Period20/04/0924/04/09

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  • Cite this

    Wu, K-C., & Marculescu, D. (2009). Joint logic restructuring and pin reordering against NBTI-induced performance degradation. In Proceedings - 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 (pp. 75-80). [5090636] (Proceedings -Design, Automation and Test in Europe, DATE). https://doi.org/10.1109/DATE.2009.5090636