JAIP-MP: A four-core Java application processor

Chun-Jen Tsai, Tsung Han Wu, Hung Cheng Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we present the design of a four-core Java application processor, JAIP-MP. Each processor core in JAIP-MP is a hardwired Java core that supports dynamic class loading, two-fold bytecode execution, object-oriented dynamic resolution, method and object caching, Java exception handling, and temporal multithreading. For JAIP-MP, a global load-balancing task manager is used to evenly distribute Java threads among the local task queues of every processor cores. In addition, a data coherence controller is designed to enforce coherence across all data caches and to perform synchronization operations among Java threads of all processor cores. Since thread management and synchronization mechanisms are completely implemented in hardware, the single-core multi-tasking performance of JAIP-MP is much higher than that of a software-based VM running on a traditional OS kernel such as Linux. For execution of multithreading applications, the speedup of a four-core JAIP-MP system can be up to 3.69 times faster than a single-core JAIP system, tested using the JemBench parallel benchmark programs.

Original languageEnglish
Title of host publication2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
PublisherIEEE Computer Society
Pages189-194
Number of pages6
ISBN (Electronic)9781467391405
DOIs
StatePublished - 30 Oct 2015
Event23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 - Daejeon, Korea, Republic of
Duration: 5 Oct 20157 Oct 2015

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume2015-October
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Conference

Conference23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015
CountryKorea, Republic of
CityDaejeon
Period5/10/157/10/15

Keywords

  • cache coherence
  • embedded SoC
  • hardwired multi-threading
  • Java processor
  • multi-core

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