Iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

Juinn-Dar Huang*, Jing Yang Jou, Wen Zen Shen

*Corresponding author for this work

Research output: Contribution to journalConference article

9 Scopus citations

Abstract

In this paper, we propose an iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. First, it finds an area-optimized performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions, the area-optimized one and the performance-optimized one, produced by our algorithm outperform the results of most existing algorithms. Therefore, our algorithm is very useful for the timing driven FPGA synthesis.

Original languageEnglish
Pages (from-to)13-17
Number of pages5
JournalIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design - San Jose, CA, USA
Duration: 10 Nov 199614 Nov 1996

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