I/O device drain engineering for a 5V 0.6um CMOS technology

Y. Wei; Y. Loh; C. Wang; Chen-Ming Hu

doi:10.1109/VTSA.1993.263616

I/O device drain engineering for a 5V 0.6um CMOS technology

Y. Wei, Y. Loh, C. Wang, Chen-Ming Hu

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.

Original language	English
Title of host publication	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	6-10
Number of pages	5
ISBN (Electronic)	0780309782
DOIs	https://doi.org/10.1109/VTSA.1993.263616
State	Published - 1 Jan 1993
Event	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan Duration: 12 May 1993 → 14 May 1993

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Conference

Conference	1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
Country	Taiwan
City	Taipei
Period	12/05/93 → 14/05/93

Access to Document

10.1109/VTSA.1993.263616

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Wei, Y., Loh, Y., Wang, C., & Hu, C-M. (1993). I/O device drain engineering for a 5V 0.6um CMOS technology. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers (pp. 6-10). [263616] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.1993.263616

Wei, Y. ; Loh, Y. ; Wang, C. ; Hu, Chen-Ming. / I/O device drain engineering for a 5V 0.6um CMOS technology. 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. pp. 6-10 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

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abstract = "The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.",

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Wei, Y, Loh, Y, Wang, C & Hu, C-M 1993, I/O device drain engineering for a 5V 0.6um CMOS technology. in 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers., 263616, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 6-10, 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993, Taipei, Taiwan, 12/05/93. https://doi.org/10.1109/VTSA.1993.263616

I/O device drain engineering for a 5V 0.6um CMOS technology. / Wei, Y.; Loh, Y.; Wang, C.; Hu, Chen-Ming.

1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 1993. p. 6-10 263616 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The ESD robustness of LATID (Large Angle Tilted Implanted Drain) MOSFET for I/O drivers is evaluated and found inadequate for deep submicron 5V CMOS technology. Alternative drain structures are examined and reported to meet the ESD and other criteria. An additional phosphorous implant that creates a LATID/DDD (Double Diffused Drain) structure meets all ESD and device criteria.

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Wei Y, Loh Y, Wang C, Hu C-M. I/O device drain engineering for a 5V 0.6um CMOS technology. In 1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 1993. p. 6-10. 263616. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.1993.263616