Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology

Yu Da Shiu*, Che Hao Chuang, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
Pages56-57
Number of pages2
DOIs
StatePublished - 1 Dec 2006
Event2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan
Duration: 24 Apr 200626 Apr 2006

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
CountryTaiwan
CityHsinchu
Period24/04/0626/04/06

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