Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology

Yu Da Shiu; Che Hao Chuang; Ming-Dou Ker

doi:10.1109/VTSA.2006.251064

Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology

Yu Da Shiu^*, Che Hao Chuang, Ming-Dou Ker

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.

Original language	English
Title of host publication	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers
Pages	56-57
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2006.251064
State	Published - 1 Dec 2006
Event	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Hsinchu, Taiwan Duration: 24 Apr 2006 → 26 Apr 2006

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference	2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA
Country	Taiwan
City	Hsinchu
Period	24/04/06 → 26/04/06

Access to Document

10.1109/VTSA.2006.251064

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Shiu, Y. D., Chuang, C. H., & Ker, M-D. (2006). Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology. In 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers (pp. 56-57). [4016600] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2006.251064

Shiu, Yu Da ; Chuang, Che Hao ; Ker, Ming-Dou. / Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology. 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. pp. 56-57 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

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abstract = "An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.",

author = "Shiu, {Yu Da} and Chuang, {Che Hao} and Ming-Dou Ker",

year = "2006",

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language = "English",

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series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

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Shiu, YD, Chuang, CH & Ker, M-D 2006, Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology. in 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers., 4016600, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, pp. 56-57, 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA, Hsinchu, Taiwan, 24/04/06. https://doi.org/10.1109/VTSA.2006.251064

Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology. / Shiu, Yu Da; Chuang, Che Hao; Ker, Ming-Dou.

2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. p. 56-57 4016600 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.

AB - An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-μm salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is fully process compatible to general CMOS process without extra process modification.

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Shiu YD, Chuang CH, Ker M-D. Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-μm CMOS technology. In 2006 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA - Proceedings of Technical Papers. 2006. p. 56-57. 4016600. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2006.251064