Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker*, K. K. Hong, T. Y. Chen, H. Tang, S. C. Huang, S. S. Chen, C. T. Huang, M. C. Wang, Y. T. Loh

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

Original languageEnglish
Pages41-44
Number of pages4
StatePublished - 1 Jan 2001
Event2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan
Duration: 18 Apr 200120 Apr 2001

Conference

Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
CountryTaiwan
CityHsinchu
Period18/04/0120/04/01

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