Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Chun Yu Lin*, Tang Long Chang, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Among three chip-level electrostatic discharge (ESD) test standards, which were human-body model (HBM), machine model (MM), and charged-device model (CDM), the CDM ESD events became critical due to the larger and faster discharging currents. Besides input/output (I/O) circuits which were connected to I/O pads, core circuits also suffered from CDM ESD events caused by coupled currents between I/O lines and core lines. In this work, the CDM ESD robustness of the core circuits with and without inserting shielding lines were investigated in a 65-nm CMOS process. Verified in a silicon chip, the CDM ESD robustness of the core circuits with shielding lines were degraded. The failure mechanism of the test circuits was also investigated in this work.

Original languageEnglish
Pages (from-to)2627-2631
Number of pages5
JournalMicroelectronics Reliability
Volume52
Issue number11
DOIs
StatePublished - 1 Nov 2012

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