Investigation of Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25- μm 60-V/5-V BCD Technology

Chia Tsen Dai*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this brief. Owing to multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon-controlled rectifier path featuring a very low holding voltage is found in the experimental silicon chip. Such a parasitic path is first reported in the literature. It may influence the electrostatic discharge robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at the HV and LV interface should be carefully defined to avoid the occurrence of an unexpected parasitic path.

Original languageEnglish
Article number7967689
Pages (from-to)3519-3523
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume64
Issue number8
DOIs
StatePublished - 1 Aug 2017

Keywords

  • Electrostatic discharge (ESD)
  • latchup
  • silicon-controlled rectifier (SCR)

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