Investigation of robust fully-silicided NMOSFETs for Sub-100 nm ESD protection circuits design

Jam Wem Lee*, Howard Tang, Yi-Ming Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper demonstrates a fully-silicided ESD protection device design in sub-100nm integrated circuits. No drain ballast resistor required is the most significant feature that makes the new device differ form the conventional ones. Accordingly, a simplified manufacturing process and a reduced device area could be obtained simultaneously. It is believed that the achievements are caused from the floating charge effects during the ESD stressed. On the other hand, in avoiding the device function affected by the floating charges, a switch is incorporated at the body electrode. The newly designed device structure is very attractive in novel ESD design for the consideration of its low cost, small size and high efficiency.

Original languageEnglish
Title of host publication2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
EditorsM. Laudon, B. Romanowicz
Pages194-197
Number of pages4
StatePublished - 2004
Event2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 - Boston, MA, United States
Duration: 7 Mar 200411 Mar 2004

Publication series

Name2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
Volume3

Conference

Conference2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004
CountryUnited States
CityBoston, MA
Period7/03/0411/03/04

Keywords

  • Efficiency
  • ESD protection
  • Floating body design
  • Fully-silicided
  • Thin gate-oxide
  • Turn on resistance
  • Turn on voltage

Fingerprint Dive into the research topics of 'Investigation of robust fully-silicided NMOSFETs for Sub-100 nm ESD protection circuits design'. Together they form a unique fingerprint.

Cite this