Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

Dennis Sylvester*, James C. Chen, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

69 Scopus citations

Abstract

This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.

Original languageEnglish
Pages (from-to)449-453
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume33
Issue number3
DOIs
StatePublished - 1 Mar 1998

Keywords

  • CMOS integrated circuits
  • Capacitance measurement
  • Integrated circuit interconnections
  • Integrated circuits measurements
  • Monitoring
  • Test structures

Fingerprint Dive into the research topics of 'Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation'. Together they form a unique fingerprint.

Cite this