This paper examines the recently introduced Charge-Based Capacitance Measurement (CBCM) technique through use of a 3-D interconnect simulator. This method is shown to have several advantages over extensive computer simulation in determining parasitic interconnect capacitances, which are the dominant source of delay in modern circuits. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
Duration: 5 May 1997 → 8 May 1997