Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and 3-D simulation

Dennis Sylvester*, James C. Chen, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

5 Scopus citations

Abstract

This paper examines the recently introduced Charge-Based Capacitance Measurement (CBCM) technique through use of a 3-D interconnect simulator. This method is shown to have several advantages over extensive computer simulation in determining parasitic interconnect capacitances, which are the dominant source of delay in modern circuits. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.

Original languageEnglish
Pages (from-to)491-494
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 1 Jan 1997
EventProceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 5 May 19978 May 1997

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