Electrostatic discharge (ESD) robustness of low-voltage (LV) field-oxide devices in stacked configuration for high-voltage (HV) applications was investigated in a 0.5-μm HV silicon on insulator (SOI) process. Stacked LV field-oxide devices with different stacking numbers have been verified in a silicon chip to exhibit both a high ESD robustness and latch-up immunity for HV applications. The effect of turn-on resistance in the stacked ESD protection device on ESD current waveform under human body model (HBM) and machine model (MM) ESD tests was studied. The resistance of stacked device has a significant impact on the ESD peak current and damping waveform, especially in MM ESD test. The MM ESD level can be increased by the numbers of LV field-oxide devices in stacked configuration, but the HBM ESD level is still kept the same. The mechanism to cause such a result has been theoretically analyzed in detail in this paper.
- Damping effect
- electrostatic discharge (ESD) protection
- high-voltage (HV) ICs
- human body model (HBM)
- machine model (MM)