This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (∼95% for L = 20 μ;m) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.
- Capacitance-voltage (C-V)
- Intrinsic input resistance
- Metal-oxide- emiconductor (MOS) capacitance
- Ultrathin gate oxide