Investigation of analogue performance for process-induced-strained PMOSFETs

Jack J.Y. Kuo*, William P.N. Chen, Pin Su

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

This paper investigates the analogue performance of process-induced- strained PMOSFETs for system-on-a chip applications. Through a comparison between co-processed strained and unstrained PMOSFETs regarding important analogue metrics such as transconductance to drain current ratio (g m/Id), output resistance, dc gain and the gain-bandwidth product, the impact of process-induced uniaxial strain on the analogue performance of MOS devices has been assessed and analysed. Our study may provide insights for analogue design using advanced strained devices.

Original languageEnglish
Article number019
Pages (from-to)404-407
Number of pages4
JournalSemiconductor Science and Technology
Volume22
Issue number4
DOIs
StatePublished - 1 Apr 2007

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