Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling

Ming Long Fan, Vita Pi Ho Hu, Yin Nien Chen, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this work, we comprehensively investigate the impact of interlayer coupling on monolithic 3D logic circuits and 6T SRAM cells using TCAD mixed-mode simulations. In addition to reduced interconnection length, monolithic 3D integration enables further performance enhancements with optimal layout. Our study indicates that minimum leakage, equivalent to the planar 2D circuits with dual reverse body biases, is achievable for circuits stacked in 3D fashion. Moreover, stacking NFET layer over the PFET tier facilitates larger design margins for SRAM cell stability and performance.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1130-1133
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

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    Fan, M. L., Hu, V. P. H., Chen, Y. N., Su, P., & Chuang, C. T. (2014). Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1130-1133). [6865339] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865339