Intrinsic reliability projections for a thin jvd silicon nitride gate dielectric in p-mosfet

Igor Polishchuk*, Qiang Lu, Yee Chia Yeo, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

A comprehensive study of the intrinsic reliability of a 1.4-nni (equivalent oxide thickness) JVD Si3N4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As the result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si3 N4 gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability.

Original languageEnglish
Pages (from-to)4-8
Number of pages5
JournalIEEE Transactions on Device and Materials Reliability
Volume1
Issue number1
DOIs
StatePublished - 1 Dec 2001

Keywords

  • Dielectric wearout
  • JVD silicon nitride
  • Lifetime projections
  • Stress-induced leakage current
  • Trap generation

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