Intra-field gate CD variability and its impact on circuit performance

Michael Orshansky*, Linda Milor, Ly Nguyen, Gene Hill, Yeng Peng, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations


Statistical analysis of an advanced CMOS process reveals a significant systematic within-field variability of gate CD strongly dependent on the local layout patterns. We present a novel modeling methodology for accurate prediction of the effect of such CD variability on circuit performance that enables statistical design for increased performance and yield. We also propose a mask-level gate CD correction algorithm allowing significant reduction of overall variability and provide a model to evaluate the effectiveness of correction.

Original languageEnglish
Pages (from-to)479-482
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
StatePublished - 1 Dec 1999
Event1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA
Duration: 5 Dec 19998 Dec 1999

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