Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems

Hao-Chiao Hong*, Chih Ko Yang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Mass-storage systems made of multi-level cell (MLC) NAND flash memory are cost effective but suffer from limited sequential write throughput. Although conventional interleaved write scheme helps, the unique characteristic of the MLC that the write time of a least significant bit (LSB) is much shorter than that of a most significant bit (MSB) leaves performance improvement headroom. This article presents an interleaved write scheme for improving the sequential write throughput of the multi-chip MLC NAND flash memory system. It leverages the longer write time of the upper pages to transmit more data by reordering the interleaved write sequence of the MLC chips. The proposed scheme can be directly implemented in the firmware of the flash memory controller without conflicting with existing flash translation layer (FTL) routines. No hardware modification is needed. The design criteria and performance improvements of general MLC NAND flash storage systems are derived for optimizing the system's performance. Experimental results of an example single-channel 4-chip solid-state drives (SSD) system showed the sequential write throughput was improved by over 11.4%. The proposed interleaved write scheme can be applied to multi-channel storage systems to improve their sequential write throughput as well.

Original languageEnglish
Article number9172126
Pages (from-to)4946-4959
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume67
Issue number12
DOIs
StatePublished - Dec 2020

Keywords

  • firmware
  • flash controller
  • FTL
  • interleaved write scheme
  • MLC
  • NAND flash memory
  • write throughput

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