An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO2 interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In experiment, a 0.5 μm n-MOSFET was subject to hot carrier stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsible for the leakage current at a large drain-to-gate bias (Vdg). The lateral field plays a dominant role in the two-step tunneling process. As Vdg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low Vdg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron hole pairs through traps is dominant.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1994|
|Event||Proceedings of the 1994 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 11 Dec 1994 → 14 Dec 1994