Interface Trap Effect on Gate Induced Drain Leakage Current in Submicron N-MOSFET’s

Ta-Hui Wang, Chimoon Huang, T. E. Chang, C. Y. Chang

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 µm LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress. The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of Aid = Aexp(—Bit / F) with a value of Bitof 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.

Original languageEnglish
Pages (from-to)2475-2477
Number of pages3
JournalIEEE Transactions on Electron Devices
Volume41
Issue number12
DOIs
StatePublished - 1 Jan 1994

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