Interface state generation under long-term positive-bias temperature stress for a p+ poly gate MOS structure

Yoichi Hiruta, Fumitomo Matsuoka, Kenji Maeguchi, Hiroshi Iwai, Kaoru Hama, Koichi Kanzaki

Research output: Contribution to journalArticlepeer-review

23 Scopus citations

Abstract

Long-term reliability for a p+ poly gate MOS structure was tested under low electric field bias temperature (BT) stress in comparison with an n+ poly gate. A significant increase in interface state density was observed for the p+ poly gate MOS structure under positive bias conditions. This phenomenon was not observed in the n+ poly gate case. The mechanism for this interface state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and hole injection from the gate electrode, were considered. All of the causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p+ poly gate is a possible cause, which could explain the interface state generation under positive-bias temperature test. For applying a p+ poly gate to CMOS structures, care should be taken when positive bias is applied to the gate electrode.

Original languageEnglish
Pages (from-to)1732-1739
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume36
Issue number9
DOIs
StatePublished - Sep 1989

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