Interface discrete trap induced variability for negative capacitance FinFETs

Ho Pei Lee*, Kuei Yang Tseng, Pin Su

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one major concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).

Original languageEnglish
Title of host publication2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
ISBN (Electronic)9781538648254
DOIs
StatePublished - 3 Jul 2018
Event2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018 - Hsinchu, Taiwan
Duration: 16 Apr 201819 Apr 2018

Publication series

Name2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018

Conference

Conference2018 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2018
CountryTaiwan
CityHsinchu
Period16/04/1819/04/18

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