Interface and electrical properties of La-silicate for direct contact of high-k with silicon

K. Kakushima*, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

42 Scopus citations

Abstract

Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48 nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μeff) has been observed. A high μeff of 300 cm2/V s with relatively low interfacial state density (Dit) of 1011 cm-2/eV can be achieved when annealed at 500 °C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2 nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in Dit and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation.

Original languageEnglish
Pages (from-to)715-719
Number of pages5
JournalSolid-State Electronics
Volume54
Issue number7
DOIs
StatePublished - Jul 2010

Keywords

  • Effective mobility
  • High-k gate dielectric
  • Rare earth oxide
  • Silicate
  • X-ray photoelectron spectroscopy

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