Interconnect scaling: Signal integrity and performance in future high-speed CMOS designs

Dennis Sylvester*, Chen-Ming Hu, O. Sam Nakagawa, Soo Young Oh

*Corresponding author for this work

Research output: Contribution to journalConference article

38 Scopus citations

Abstract

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 μm generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.

Original languageEnglish
Pages (from-to)42-43
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Jan 1998
EventProceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 9 Jun 199811 Jun 1998

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