Integration of high-k gate stack systems into planar CMOS process flows

H. R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P. J. Chen, P. Lysaght, B. Nguyen, J. E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G. A. Brown, C. Young, B. ForanF. Shaapur, Tuo-Hung Hou, C. Lim, H. Alshareef, S. Borthakur, D. J. Derro, R. Bergmann, L. A. Larson, M. I. Gardner, J. Gutt, R. W. Murto, K. Torres, M. D. Jackson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

Original languageEnglish
Title of host publicationExtended Abstracts of International Workshop on Gate Insulator, IWGI 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2-11
Number of pages10
ISBN (Electronic)4891140216, 9784891140212
DOIs
StatePublished - 1 Jan 2001
EventInternational Workshop on Gate Insulator, IWGI 2001 - Tokyo, Japan
Duration: 1 Nov 20012 Nov 2001

Publication series

NameExtended Abstracts of International Workshop on Gate Insulator, IWGI 2001

Conference

ConferenceInternational Workshop on Gate Insulator, IWGI 2001
CountryJapan
CityTokyo
Period1/11/012/11/01

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