Integrated tungsten chemical mechanical polishing process characterization for via plug interconnection in ultralarge scale integrated circuits

Chin Kun Wang*, Hua Shu Wu, Nai Tien Ou, Huang-Chung Cheng

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

One integrated tungsten (W) chemical mechanical polishing (CMP) process characterization with wide production margin is developed for W plug application in sub-quarter micron technology. In this study, it is identified that donut-type function failure and reliability degradation on a designed application specific integrated circuit (ASIC) product vehicle result from an extra oxide layer atop the W plugs. W recess in via holes makes the plugs more vulnerable to oxide layer formation. CMP polish rate uniformity, layout dependence of via holes and queue-time (Q-time) control between WCMP and post-cleaning treatment are key parameters for preventing failure from interfacial oxide layer. Integrated optimization of WCMP process combined with W extrusion by a slight oxide polish immediately after WCMP is proposed to achieve a robust W plug process. Significant yield improvement from 45% to 82% in wafer edge region and 0% failure in three qualification lots in a product reliability test are demonstrated.

Original languageEnglish
Pages (from-to)5120-5124
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume41
Issue number8
DOIs
StatePublished - 1 Aug 2002

Keywords

  • ASIC
  • Layout dependence
  • W extrusion
  • W plug
  • WCMP

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