Integrated power transistor in 0.18-μm CMOS technology for RF system-on-chip applications

Heng Ming Hsu*, Jiong Guang Su, Chih Wei Chen, Denny D. Tang, Chun Hsiung Chen, Jack Yuan Chen Sun

*Corresponding author for this work

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

A novel design and performance of a power MOS transistor for RF system-on-chip applications are reported. The power MOS transistor with high breakdown voltage is integrated into 0.18-μm CMOS technology with only one additional mask. By an optimized design considering all aspects of dc and RF performances, a power MOS transistor with 16-GHz cutoff frequency and 24-GHz maximum oscillation frequency has been demonstrated. In addition, the power gain is 12 dB at 2.4 GHz with power-added efficiency of 50%. In this study, the device architectures that include drain engineering, substrate engineering, and gate scaling are investigated comprehensively.

Original languageEnglish
Pages (from-to)2873-2881
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Volume50
Issue number12
DOIs
StatePublished - Dec 2002

Keywords

  • 0.18-μm CMOS
  • RF power MOS transistor
  • System-on-chip (SoC)

Fingerprint Dive into the research topics of 'Integrated power transistor in 0.18-μm CMOS technology for RF system-on-chip applications'. Together they form a unique fingerprint.

Cite this