Integrated power supply planning and floorplanning

I. Min Liu, Hung-Ming Chen, Tan Li Chou, A. Aziz, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply voltage can result in slower cell switching, or even circuit failure. Nevertheless, most floorplanning methodologies have ignored power supply considerations. Thus, the resulting floorplan may suffer from local hot spots and insufficient power supply for certain circuit blocks. In this paper, we present an optimal power supply planning algorithm based on network flow to shorten the current paths from power bumps to local power supply wirings. We have incorporated our algorithm into a floorplanning algorithm for integrated floorplanning and power supply planning. Experimental results are encouraging.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages589-594
Number of pages6
ISBN (Electronic)0780366336
DOIs
StatePublished - 1 Jan 2001
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: 30 Jan 20012 Feb 2001

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Conference

ConferenceAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period30/01/012/02/01

Keywords

  • Circuit noise
  • Design engineering
  • Noise reduction
  • Power engineering and energy
  • Power engineering computing
  • Power supplies
  • Routing
  • Switching circuits
  • Very large scale integration
  • Voltage

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