Instruction set extension generation with considering physical constraints

I. Wei Wu*, Shih Chia Huang, Chung-Ping Chung, Jyh-Jiun Shann

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations


In this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.

Original languageEnglish
Title of host publicationHigh Performance Embedded Architectures and Compilers - Second International Conference, HiPEAC 2007, Proceedings
Number of pages15
StatePublished - 1 Dec 2007
Event2nd International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2007 - Ghent, Belgium
Duration: 28 Jan 200730 Jan 2007

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4367 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference2nd International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2007


  • ASIP
  • Extensible processors
  • Instruction set extension
  • Pipestage timing constraint

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