Instruction cache prefetching with extended BTB

Shyh An Chi*, R. Ming Shiu, Jih Ching Chiu, Si En Chang, Chung-Ping Chung

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determines the target line to be prefetched based on the current fetched line address. However, as the cache line becomes wider, there may be multiple branches in a cache line which hurdles the decision made by these methods. This paper develops a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches. We call it the branch instruction based (BIB) prefetching. In BIB prefetching, the prefetch information is recorded in an extended BTB. Simulation results show that, the BIB prefetching outperforms the traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average. As the BTB designs become more sophisticated and achieve higher hit and accuracy ratio, the BIB prefetching can achieve higher performance.

Original languageEnglish
Pages360-365
Number of pages6
DOIs
StatePublished - 1 Dec 1997
EventProceedings of the 1997 International Conference on Parallel and Distributed Systems - Seoul, South Korea
Duration: 10 Dec 199713 Dec 1997

Conference

ConferenceProceedings of the 1997 International Conference on Parallel and Distributed Systems
CitySeoul, South Korea
Period10/12/9713/12/97

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