Influence of postdeposition annealing on physical and electrical properties of high-k Yb2TiO5 gate dielectrics

Tung Ming Pan*, Li Chen Yen, Chien Hung Chiang, Tien-Sheng Chao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The structure and electrical properties of a high-k Yb2TiO 5 gate dielectric deposited on Si(100) substrates through reactive cosputtering were investigated. X-ray diffraction, X-ray photoelectron spectroscopy and atomic force microscopy were used to study the morphological and chemical features of these films as functions of the growth conditions. The Yb2TiO5 dielectrics annealed at 800°C exhibited a thinner capacitance equivalent thickness, a lower gate leakage current, a smaller density of interface state, and a relatively lower hysteresis voltage compared to those at other annealing temperatures. These results are attributed to the formation of a rather well-crystallized Yb2TiO5 structure and composition.

Original languageEnglish
Title of host publicationAdvanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6
Subtitle of host publicationNew Materials, Processes, and Equipment
Pages247-252
Number of pages6
Edition1
DOIs
StatePublished - 30 Dec 2010
EventAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting - Vancouver, BC, Canada
Duration: 26 Apr 201027 Apr 2010

Publication series

NameECS Transactions
Number1
Volume28
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferenceAdvanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting
CountryCanada
CityVancouver, BC
Period26/04/1027/04/10

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