Satisfying timing requirements is the most challenging phase of the modern complex system-on-chip (SOC) design. The timing closure of the static timing analysis (STA) is a necessary but time-consuming stage before tapeout. Physical design tools are normally ineffective in obtaining accurate timing estimates, so the accurate timing calculation must be conducted in the signoff level timer after each physical modification on designs. This paper proposes a way to reduce the number of iterations between the signoff timer and the physical implementation procedures. Approximate timing models for extracting the signoff timer information and the nonlinear library are used in the optimization of the timing-driven placement (TDP). The accurate estimation of net and cell delays is integrated into TDP, so the optimal positions of cell movement can be obtained. This postoptimization algorithm was entered into the benchmark of the ICCAD15 incremental timing-driven contest, and the embodiments were obtained from the top three teams. Under the same design constraints, the proposed method yielded significant improvements in all kinds of default design chip.
|Number of pages||13|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Oct 2019|
- Physical design
- timing optimization
- timing-driven placement (TDP)