Incremental ADC with parallel counting

Tao He, Chia-Hung Chen, Yi Zhang, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step topologies. Also, the parallel counting technique can be implemented with different IADC topologies.

Original languageEnglish
Title of host publication2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1017-1020
Number of pages4
ISBN (Electronic)9781509063895
DOIs
StatePublished - 27 Sep 2017
Event60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: 6 Aug 20179 Aug 2017

Publication series

NameMidwest Symposium on Circuits and Systems
Volume2017-August
ISSN (Print)1548-3746

Conference

Conference60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
CountryUnited States
CityBoston
Period6/08/179/08/17

Keywords

  • Analog-to-digital converter
  • Delta sigma modulator
  • Extended data converters
  • High resolution
  • Incremental data converters
  • Sensor interfaces
  • Ultra-low-power

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