In-placement clock-tree aware multi-bit flip-flop generation for power optimization

Chih Cheng Hsu, Yu Chuan Chen, Po-Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

18 Scopus citations

Abstract

Utilizing multi-bit flip-flops (MBFFs) is one of the most effective power optimization techniques in modern nanometer integrated circuit (IC) design. Most of the previous work apply MBFFs without doing placement refinement of combinational logic cells. Such problem formulation may result in less power reduction due to tight timing constraints with fixed combinational logic cells. This paper introduces a novel placement flow with clock-tree aware flip-flop merging and MBFF generation, and proposes the corresponding algorithms to simultaneously minimize flip-flop power and clock latency when applying MBFFs during placement. Experimental results based on the IWLS-2005 benchmark show that our approach is very effective in not only flip-flop power but also clock latency minimization without degrading circuit performance. To our best knowledge, this is also the first work in the literature which considers clock trees during flip-flop merging and MBFF generation.

Original languageEnglish
Title of host publication2013 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - Digest of Technical Papers
Pages592-598
Number of pages7
DOIs
StatePublished - 1 Dec 2013
Event2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013 - San Jose, CA, United States
Duration: 18 Nov 201321 Nov 2013

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Conference

Conference2013 32nd IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2013
CountryUnited States
CitySan Jose, CA
Period18/11/1321/11/13

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