Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers

S. H. Lin; H. J. Yang; W. B. Chen; F. S. Yeh; Sean P. McAlister; Albert Chin

doi:10.1109/TED.2008.924435

Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers

S. H. Lin^*, H. J. Yang, W. B. Chen, F. S. Yeh, Sean P. McAlister, Albert Chin

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

We have studied the performance of double-quantum-barrier [TaN - Ir ₃ Si] - [HfAlO - LaAlO ₃ ] - Hf _0.3 N _0.2 O _0.5 - [HfAlO - SiO ₂ -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.

Original language	English
Pages (from-to)	1708-1713
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	7
DOIs	https://doi.org/10.1109/TED.2008.924435
State	Published - 1 Jul 2008

Keywords

Erase
High-k
Nonvolatile memory
Program

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10.1109/TED.2008.924435

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title = "Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers",

abstract = " We have studied the performance of double-quantum-barrier [TaN - Ir 3 Si] - [HfAlO - LaAlO 3 ] - Hf 0.3 N 0.2 O 0.5 - [HfAlO - SiO 2 -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.",

keywords = "Erase, High-k, Nonvolatile memory, Program",

author = "Lin, {S. H.} and Yang, {H. J.} and Chen, {W. B.} and Yeh, {F. S.} and McAlister, {Sean P.} and Albert Chin",

year = "2008",

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doi = "10.1109/TED.2008.924435",

language = "English",

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publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

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AU - Lin, S. H.

AU - Yang, H. J.

AU - Chen, W. B.

AU - Yeh, F. S.

AU - McAlister, Sean P.

AU - Chin, Albert

PY - 2008/7/1

Y1 - 2008/7/1

N2 - We have studied the performance of double-quantum-barrier [TaN - Ir 3 Si] - [HfAlO - LaAlO 3 ] - Hf 0.3 N 0.2 O 0.5 - [HfAlO - SiO 2 -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.

AB - We have studied the performance of double-quantum-barrier [TaN - Ir 3 Si] - [HfAlO - LaAlO 3 ] - Hf 0.3 N 0.2 O 0.5 - [HfAlO - SiO 2 -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.

KW - Erase

KW - High-k

KW - Nonvolatile memory

KW - Program

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