Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers

S. H. Lin*, H. J. Yang, W. B. Chen, F. S. Yeh, Sean P. McAlister, Albert Chin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

We have studied the performance of double-quantum-barrier [TaN - Ir 3 Si] - [HfAlO - LaAlO 3 ] - Hf 0.3 N 0.2 O 0.5 - [HfAlO - SiO 2 -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.

Original languageEnglish
Pages (from-to)1708-1713
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume55
Issue number7
DOIs
StatePublished - 1 Jul 2008

Keywords

  • Erase
  • High-k
  • Nonvolatile memory
  • Program

Fingerprint Dive into the research topics of 'Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers'. Together they form a unique fingerprint.

Cite this