Abstract
We have studied the performance of double-quantum-barrier [TaN - Ir 3 Si] - [HfAlO - LaAlO 3 ] - Hf 0.3 N 0.2 O 0.5 - [HfAlO - SiO 2 -Si charge-trapping memory devices. These devices display good characteristics in terms of their ±9-V program/erase (P/E) voltage, 100-μs P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 °C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced interface trap generation.
Original language | English |
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Pages (from-to) | 1708-1713 |
Number of pages | 6 |
Journal | IEEE Transactions on Electron Devices |
Volume | 55 |
Issue number | 7 |
DOIs | |
State | Published - 1 Jul 2008 |
Keywords
- Erase
- High-k
- Nonvolatile memory
- Program