Improving the electrical characteristics of MOS transistors with CeO 2/La 2O 3 stacked gate dielectric

B. L. Yang, H. Wong*, K. Kakushima, H. Iwai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

15 Scopus citations


In this work, the electrical characteristics of MOSFETs with CeO 2/La 2O 3 gate dielectric stacks, where it was shown to have much lower amount of oxygen vacancy, were studied. We found that the negative threshold voltage shift in the La 2O 3-only transistors can be significantly suppressed. This improvement is attributed to the reduction of oxide charge density and to the dipole at the Si/La 2O 3 interface. Significant enhancement in channel mobility was also found for both NMOS and PMOS transistors. This latter improvement should be due to the silicon oxidation taking place at the La 2O 3/Si interface with the available of extra oxygen atoms from the CeO 2 layer. We further found that the subthreshold slopes for NMOS and PMOS transistors with 2.5 μm gate length were reduced to about 72 mV/dec, which are significantly smaller than those of transistors without using CeO 2 capping layer. This observation further confirms that the CeO 2 capping layer also affects the La 2O 3/Si interface properties.

Original languageEnglish
Pages (from-to)1613-1616
Number of pages4
JournalMicroelectronics Reliability
Issue number8
StatePublished - Aug 2012

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