Improving electrical performance of the scaled low-temperature poly-si thin film transistors using vacuum encapsulation technique

Wei Kai Lin*, Ta Chuan Liao, Chun Yu Wu, Shih Wei Tu, Yen Ting Liu, Jun Quan Lin, Huang-Chung Cheng, Feng Tso Chien, Wan Lu Chen, Chii Wen Chen, Ya-Hsiang Tai

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH 4 -based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain junction.

Original languageEnglish
Pages (from-to)1192-1195
Number of pages4
JournalDigest of Technical Papers - SID International Symposium
Volume39
Issue number3
DOIs
StatePublished - 30 Oct 2008
Event2008 SID International Symposium - Los Angeles, CA, United States
Duration: 20 May 200821 May 2008

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