Improving design verifiability by early RTL coverability analysis

Kai Hui Chang*, Chia Wei Chang, Jie Hong Roland Jiang, Chien-Nan Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Achieving high coverage is an important goal in design verification. Fixing coverability problems found at the verification stage, however, can require tremendous effort. To address this problem, we propose a flow for analyzing code and variable-toggle coverability at the early-RTL block-level stage. In addition, we devise a novel technique to analyze the coverability problems so that engineers can resolve the issues more efficiently. By identifying coverability problems at early RTL design stages, design verifiability can be improved, thus reducing the effort required at the verification phase.

Original languageEnglish
Title of host publication10th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2012
Pages25-32
Number of pages8
DOIs
StatePublished - 12 Oct 2012
Event10th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2012 - Arlington, VA, United States
Duration: 16 Jul 201217 Jul 2012

Publication series

Name10th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2012

Conference

Conference10th ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2012
CountryUnited States
CityArlington, VA
Period16/07/1217/07/12

Keywords

  • Coverage
  • Satisfiability
  • Verification

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