Improvements of Fermi-level pinning and NBTI by fluorinated HfO 2-CMOS

Chao Sung Lai, Woei Cherng Wu, Huai Hsien Chiu, Jer Chyi Wang, Pai Chi Chou, Tien-Sheng Chao*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Improvement of Fermi-level pinning (FLP) and relaxation of negative-bias-temperature-instability (NBTI) for CMOS without interfacial layers was achieved by fluorine incorporation into HfO2. The driving current capability was increased up to 48% and 45% for n-MOSFET and p-MOSFET, respectively. It's caused by the oxygen vacancy was blocked by the fluorine incorporated interface and resulted in the suppression of the interfacial oxide growth to achieved thinner effective oxide thickness (EOT). The improvement included the Fermi-level pinning shift from ∼0.1eV to ∼0.02eV for samples without and with fluorination, respectively. Vth shifts under NBTI stressing were relaxed from positive 350mv to negative 270mv for control and fluorinated samples, respectively. It is due to the Si-F bondings broken under NBTI stressing which the released-fluorine re-incorporate to passivate the HfO2 bulk.

Original languageEnglish
Title of host publication2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
DOIs
StatePublished - 1 Dec 2010
Event2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 - Hong Kong, China
Duration: 15 Dec 201017 Dec 2010

Publication series

Name2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

Conference

Conference2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
CountryChina
CityHong Kong
Period15/12/1017/12/10

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    Lai, C. S., Wu, W. C., Chiu, H. H., Wang, J. C., Chou, P. C., & Chao, T-S. (2010). Improvements of Fermi-level pinning and NBTI by fluorinated HfO 2-CMOS. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 [5713757] (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). https://doi.org/10.1109/EDSSC.2010.5713757