Improvement of SiO2/4H-SiC Interface properties by post-metallization annealing

Y. M. Lei, H. Wakabayashi, K. Tsutsui, H. Iwai, M. Furuhashi, S. Tomohisa, S. Yamakawa, K. Kakushima*

*Corresponding author for this work

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Electrical characteristics of SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO2 (ALD-SiO2) gate dielectrics were investigated. Post-metallization annealing (PMA) with W gate electrodes at 950 °C showed a large recovery in the flatband voltage toward the ideal value and the hysteresis was reduced to 36 mV. Interface state density (Dit) of 3 × 1011 cm−2/eV was obtained after the PMA for 5 × 103 s. The concentration of the residual carbon atoms in the SiO2 gate dielectrics has been reduced after annealing, suggesting one of the possible origins of the improvements.

Original languageEnglish
Pages (from-to)226-229
Number of pages4
JournalMicroelectronics Reliability
StatePublished - May 2018

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    Lei, Y. M., Wakabayashi, H., Tsutsui, K., Iwai, H., Furuhashi, M., Tomohisa, S., Yamakawa, S., & Kakushima, K. (2018). Improvement of SiO2/4H-SiC Interface properties by post-metallization annealing. Microelectronics Reliability, 84, 226-229.